The present disclosure relates to a semiconductor structure and a method of fabricating the same. More particularly, the present disclosure relates to a hybrid copper interconnect structure containing interconnect features that contain different levels of copper purity therein as well as a method of fabricating the same.
Generally, semiconductor devices include a plurality of circuits which form an integrated circuit (IC) fabricated on a semiconductor substrate. A complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the substrate. Efficient routing of these signals across the device requires formation of multilevel or multilayered schemes, such as, for example, single or dual damascene wiring structures. The wiring structure typically includes copper, Cu, since Cu based interconnects provide higher speed signal transmission between large numbers of transistors on a complex semiconductor chip as compared with aluminum, Al, based interconnects.
Within a typical interconnect structure, metal vias run perpendicular to the semiconductor substrate and metal lines run parallel to the semiconductor substrate. Further enhancement of the signal speed and reduction of signals in adjacent metal lines (known as “crosstalk”) are achieved in today's IC product chips by embedding the metal lines and metal vias (e.g., conductive features) in a dielectric material having a dielectric constant of less than 4.0.
Resistance/capacitance reduction in current Cu back-end-of-the-line (BEOL) interconnect structures is getting more and more challenging. As such, any method of reducing the resistance/capacitance within a Cu BEOL structure is needed. Also, needed are interconnect structures in which the reliable thereof is maintained or even enhanced as compared with conventional Cu BEOL interconnect structures.